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ZL50017 1 K Digital Switch
Data Sheet Features
* 1024 channel x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch at 4.096, 8.192 or 16.384 Mbps 16 serial TDM input, 16 serial TDM output streams Output streams can be configured as bidirectional for connection to backplanes Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) Per-stream input bit delay with flexible sampling point selection Per-stream output bit and fractional bit advancement Per-channel constant or variable throughput delay for frame integrity and low latency applications Per-channel high impedance output control Per-channel message mode Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz Input frame pulses:61 ns, 122 ns, 244 ns Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses Ordering Information ZL50017GAC 256-ball PBGA ZL50017QCC 256-lead LQFP -40C to +85C * * * * Connection memory block programming Supports ST-BUS and GCI-Bus standards for input and output timing IEEE-1149.1 (JTAG) test port 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage
October 2004
* * * * * *
Applications
* * * * * * * PBX and IP-PBX Small and medium digital switching platforms Remote access servers and concentrators Wireless base stations and controllers Multi service access platforms Digital Loop Carriers Computer Telephony Integration
VSS RESET ODE
* * * * *
VDD_CORE
VDD_IO
VDD_COREA
VDD_IOA
STi[15:0] FPi CKi MODE_4M0 MODE_4M1
S/P Converter
Data Memory
P/S Converter
STio[15:0] TMS
Test Port
Input Timing
Connection Memory
TDi TDo TCK TRST
Internal Registers &Microprocessor Interface
DS_RD
R/W_WR
A[13:0]
Figure 1 - ZL50017 Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
MOT_INTEL
DTA_RDY
D[15:0]
CS
ZL50017 Description
Data Sheet
The ZL50017 is a maximum 1024 x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch. It has sixteen input streams (STi0 - 15) and sixteen output streams (STio0 - 15). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. All of the input and output streams operate at the same data rate and can be programmed at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. The output streams can be configured to operate in bi-directional mode, in which case STi0 - 15 will be ignored. The device contains two types of internal memory - data memory and connection memory. There are three modes of operation - Connection Mode, Message Mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In high impedance mode the selected output channel can be put into a high impedance state. The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors. The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
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Zarlink Semiconductor Inc.
ZL50017
Data Sheet
Table of Contents
1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Input Clock (CKi) and Input Frame Pulse (FPi) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.0 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Zarlink Semiconductor Inc.
ZL50017
Data Sheet
List of Figures
Figure 1 - ZL50017 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50017 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 7 Figure 3 - ZL50017 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - Input Timing when CKIN1 - 0 bits = "10" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5 - Input Timing when CKIN1 - 0 bits = "01" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6 - Input Timing when CKIN1 - 0 = "00" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7 - Input Bit Delay Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 9 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10 - Output Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11 - Output Fractional Bit Advancement Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 15 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 16 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 17 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 18 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 19 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 20 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 21 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 22 - ST-BUS Input and Output Timing Diagram when Operated at 2, 4, 8 and 16 Mbps . . . . . . . . . . . . . . 47 Figure 23 - GCI-Bus Input and Output Timing Diagram when Operated at 2, 4, 8 and 16 Mbps . . . . . . . . . . . . . 48
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Zarlink Semiconductor Inc.
ZL50017
Data Sheet
List of Tables
Table 1 - CKi and FPi Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 4 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6 - Internal Mode Selection Register (IMS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7 - Software Reset Register (SRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8 - Data Rate Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 10 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 11 - Stream Output Control Register 0 - 15 (SOCR0 - 15) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 12 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 13 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 14 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Zarlink Semiconductor Inc.
ZL50017
1.0 Changes Summary
Item Figure 2, "ZL50017 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) Figure 3, "ZL50017 256-Lead 28 mm x 28 mm LQFP (top view) * * * * 9 27 28 3.0, "Pin Description" 13.0, "Register Address Mapping" 14.0, "Detailed Register Description" * * * Change
Data Sheet
Page 7
Re-labeled IC_OPEN to MODE_4M0 Location: Ball M14 Re-labeled IC_OPEN to MODE_4M1 Location: Ball R13 Re-labeled IC_OPEN to MODE_4M0 Location: Pin 46 Re-labeled IC_OPEN to MODE_4M1 Location: Pin 48 Added MODE_4M0 & MODE_4M1 descriptions Added Reg 0010H to list Changed Bits 6-5 Description - Added MODE 4M0/1 reference
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Zarlink Semiconductor Inc.
ZL50017
2.0
2.1
1
A
Data Sheet
Pinout Diagrams
BGA Pinout
2 NC STi10 STi9 STi11 STi14 STi15 RESET VSS VDD_IOA VSS VDD_ COREA NC NC NC NC NC 2 3 NC STi5 VSS VDD_IO STi8 STi12 4 NC STi4 STi7 STi3 VDD_IO STi13 5 NC NC STi6 STi2 VSS VDD_IO TDo NC VSS VDD_ COREA VDD_IO VSS NC STio3 NC NC 5 6 NC STi0 STi1 NC VDD_ CORE VDD_ CORE VDD_IO VSS NC VDD_IO VDD_ CORE VDD_ CORE D1 NC D2 NC 6 7 NC NC NC NC NC VDD_ CORE VSS VSS VSS VSS VDD_ CORE VDD_ CORE D5 D3 D4 NC 7 8 NC NC NC NC NC VSS VSS VSS VSS VSS VSS D6 D7 D8 D9 NC 8 9 NC VDD_ COREA VSS NC NC VSS VSS VSS VSS VSS VSS D10 D11 D14 D12 NC 9 10 NC FPi 11 NC CKi 12 NC 13 NC 14 NC 15 NC ODE STio15 STio14 NC NC NC A11 A6 A1 STio9 STio8 NC NC STio7 NC 15 16 VSS NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS 16
A
VSS NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS 1
B
IC_Open IC_Open IC_GND VSS VDD_IO STio12 NC NC NC A8 A2 STio11 MODE_ 4M0 VDD_IO VSS STio6 NC 14
B
C
IC_Open IC_Open IC_Open IC_GND VSS NC VDD_ CORE VSS VSS VSS VSS VDD_ CORE VDD_ CORE D13 NC D15 NC 10 NC VDD_ CORE VDD_ CORE VDD_IO A7 A3 VDD_IO VDD_ CORE VDD_ CORE R/W _WR STio5 CS NC 11 IC_GND VSS VDD_IO A12 A9 A4 IC_Open VDD_IO VSS DTA_ RDY NC DS_RD NC 12 STio13 VDD_IO IC_Open A13 A10 A5 A0 STio10 MOT _INTEL STio4 NC MODE_ 4M1 NC 13
C
D
D
E
E
F
F
G
IC_GND IC_Open VSS VDD_IOA TMS TRST TDi VDD_IO VSS NC NC 3 VDD_ COREA VSS VSS TCK D0 STio0 STio1 STio2 NC 4
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
T
T
Note: A1 corner identified by metallized marking. Note: Pinout is shown as viewed through top of package.
Figure 2 - ZL50017 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)
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Zarlink Semiconductor Inc.
ZL50017
2.2 QFP Pinout
Data Sheet
NC NC VDD_IO NC NC STi_8 VSS STi_9 STi_10 STi_11 STi_12 STi_13 STi_14 STi_15 VDD_IO IC_GND VSS IC_Open RESET TDo VDD_CORE VSS NC VSS VDD_COREA VSS NC VDD_IOA NC VSS VSS VDD_COREA NC VDD_IOA NC VSS NC VSS VDD_COREA VSS VDD_CORE TMS VSS NC NC TCK TRST TDi VDD_IO VSS NC NC NC NC NC NC VDD_IO NC VSS NC NC NC NC NC
194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256
192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
NC NC NC NC VSS STi_7 VDD_IO STi_6 STi_5 STi_4 STi_3 STi_2 STi_1 STi_0 VSS VDD_IO NC VSS NC VDD_CORE NC VSS NC VDD_IO NC NC NC NC NC NC VSS NC VDD_IO NC VSS VDD_COREA VSS FPi CKi IC_Open IC_Open IC_Open IC_Open IC_Open IC_GND VSS VDD_CORE VSS IC_GND VDD_IO VSS ODE NC NC NC NC NC NC NC VDD_IO NC NC NC NC
NC NC NC NC NC VSS NC VDD_IO NC NC STio_15 STio_14 STio_13 STio_12 VSS VDD_IO NC VSS NC VDD_CORE NC IC_GND NC IC_Open NC VSS NC VDD_IO NC A13 A12 VSS A11 VDD_CORE A10 A9 A8 A7 A6 A5 A4 A3 A2 VSS A1 VDD_CORE A0 VSS IC_Open VDD_IO NC NC NC NC STio_11 STio_10 STio_9 VSS STio_8 VDD_IO NC NC NC NC
NC NC NC NC VDD_IO STio_0 STio_1 VSS STio_2 STio_3 NC NC NC NC VDD_IO D0 VSS D1 VDD_CORE D2 VSS D3 D4 D5 D6 D7 D8 D9 VDD_IO D10 VSS D11 VDD_CORE D12 VSS D13 D14 D15 R/W_WR CS MOT_INTEL DS_RD NC DTA_RDY VDD_CORE MODE_4M0 VSS MODE_4M1 VDD_IO VSS STio_4 STio_5 STio_6 STio_7 NC NC
Figure 3 - ZL50017 256-Lead 28 mm x 28 mm LQFP (top view)
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Zarlink Semiconductor Inc.
VDD_IO
NC NC VSS NC NC NC NC
ZL50017
3.0 Pin Description
LQFP Pin Number 19, 33, 45, 83, 95, 109, 146, 173, 213, 233 217, 231, 157, 224 5, 15, 29, 49, 57, 69, 79, 101, 113, 121, 133, 143, 160, 169, 177, 186, 195, 207, 241, 249 220, 226 8, 17, 21, 31, 35, 47, 50, 60, 71, 81, 85, 97, 103, 111, 114, 123, 142, 145, 147, 156, 158, 162, 171, 175, 178, 188, 199, 209, 214, 216, 218, 222, 223, 228, 230, 232, 235, 242, 251 Pin Name VDD_CORE Description Power Supply for the core logic: +1.8 V
Data Sheet
PBGA Pin Number E6, E11, F6, F7, F10, F11, L6, L7, L10, L11, M6, M7, M10, M11 H4, K5, B9, L2 D3, D14, E4, E13, F5, F12, G6, G11, K6, K11, L5, L12, N3, N14
VDD_COREA VDD_IO
Power Supply for analog circuitry: +1.8 V Power Supply for I/O: +3.3 V
J2, J3 A1, A16, C3, C9, C14, D10, E5, E12, F8, F9, G7, G8, G9, G10, H2, H3, H6, H7, H8, H9, H10, J4, J5, J7, J8, J9, J10, K2, K4, K7, K8, K9, K10, L8, L9, M5, M12, P3, P14, T1, T16
VDD_IOA VSS
Power Supply for the CKo5 and CKo3 outputs: +3.3 V Ground
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Zarlink Semiconductor Inc.
ZL50017
PBGA Pin Number K3 LQFP Pin Number 234 Pin Name TMS Description
Data Sheet
Test Mode Select (5 V-Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven. Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal Pull-up) Provides the clock to the JTAG test logic. Test Reset (5 V-Tolerant Input with Internal Pull-up) Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low during power-up to ensure that the device is in the normal functional mode. When JTAG is not being used, this pin should be pulled low during normal operation. Test Serial Data In (5 V-Tolerant Input with Internal Pull-up) JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up resistor when it is not driven. Test Serial Data Out (5 V-Tolerant Three-state Output) JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. Internal Test Mode (5 V-Tolerant Input with Internal Pull-down) These pins may be left unconnected.
L4
238
TCK
L3
239
TRST
M3
240
TDi
G5
212
TDo
B12, B13, C10, C11, F13, G4, K12, C12, G3, D12, C13, B14
80, 105, 150, 151, 152, 153, 210, 149 144, 107, 148, 208
IC_Open
IC_GND
Internal Test Mode Enable (5 V-Tolerant Input) These pins MUST be low.
10
Zarlink Semiconductor Inc.
ZL50017
PBGA Pin Number A8, A9, A14, A15, E10, M2, N2, P2, P16, R2, R16, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, D16, E16, C16, B16, A13, A12, A10, A11, N1, M1, P1, R1, T2, T3, T5, T4, N16, M16, L16, K16, H16, J16, G16, F16,D9, E8, C8, E7, D6, H5, P10, G15, G14, E15, F14, H14, D11, F15, B7, C7, B5, J6, R3, P6, R5, N5, P12, N15, P13, P15, E1, D1, G1, F1, J1, H1, K1, L1, A7, A5, A6, A4, A3, A2, C1, B1, E9, D8, B8, D7 LQFP Pin Number 61, 62, 63, 64, 65, 66, 67, 68, 134, 135, 136, 137, 138, 139, 140, 215, 219, 225, 229, 236, 237, 125, 126, 127, 128, 129, 130, 131, 132, 253, 254, 255, 256, 1, 2, 3, 4, 75, 76, 77, 78, 119, 120, 122, 124,159, 163, 165, 167, 176, 221, 43, 102, 106, 110, 112, 100, 104, 108, 170, 172, 174, 227, 11, 12, 13, 14, 55, 56, 58, 59, 243, 244, 245, 246, 247, 248, 250, 252, 189, 190, 191, 192, 193, 194, 196, 197, 161, 164, 166, 168 Pin Name NC Description No Connect These pins MUST be left unconnected.
Data Sheet
11
Zarlink Semiconductor Inc.
ZL50017
PBGA Pin Number M14, R13 LQFP Pin Number 46, 48 Pin Name MODE_4M0, MODE_4M1 Description
Data Sheet
4 M Input Clock Mode 0 to 1 (5 V-Tolerant Input with internal pull-down) These two pins should be tied together. MODE _4M1
0 1 0 1
MODE _4M0
0 1 1 0
Operation CKi = 8.192 MHz or 16.384 MHz CKi = 4.096 MHz
Reserved Reserved
See Table 5, "Control Register (CR) Bits" on page 28 for CKi and FPi selection using the CKIN1 - 0 bits. B10 155 FPi ST-BUS/GCI-Bus Frame Pulse Input (5 V-Tolerant Schmitt-Triggered Input) This pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the frame boundary. The frame pulse frequency is 8 kHz. The frame pulse associated with the CKi must be applied to this pin. By default, the device accepts a negative frame pulse in ST-BUS format, but it can accept a positive frame pulse instead if the FPINP bit is set high in the Control Register (CR). It can accept a GCI-formatted frame pulse by programming the FPINPOS bit in the Control Register (CR) to high. ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt-Triggered Input) This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock. The clock frequency applied to this pin must be twice the highest input or output data rate. The exception is, when data is running at 16.384 Mbps, a 16.384 MHz clock must be used. By default, the clock falling edge defines the input frame boundary, but the device allows the clock rising edge to define the frame boundary by programming the CKINP bit in the Control Register (CR). Serial Input Streams 0 to 15 (5 V-Tolerant Inputs with Internal Pull-downs) The data rate of all the input streams are programmed through the "Data Rate Selection Register" on page 31. In the 2.048 Mbps mode, these pins accept serial TDM data streams at 2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode, these pins accept serial TDM data streams at 4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode, these pins accept serial TDM data streams at 8.192 Mbps with 128 channels per frame. In the 16.384 Mbps mode, these pins accept serial TDM data streams at 16.384 Mbps with 256 channels per frame.
B11
154
CKi
B6, C6, D5, D4, B4, B3, C5, C4, E3, C2, B2, D2, F3, F4, E2, F2
179, 180, 181, 182, 183, 184, 185, 187, 198, 200, 201, 202, 203, 204, 205, 206
STi0 - 15
12
Zarlink Semiconductor Inc.
ZL50017
PBGA Pin Number N4, P4, R4, P5, N13, P11, R14, R15, M15, L15, L13, L14, E14, D13, D15, C15 LQFP Pin Number 6, 7, 9, 10, 51, 52, 53, 54, 70, 72, 73, 74, 115, 116, 117, 118 Pin Name STio 0 - 15 Description
Data Sheet
Serial Output Streams 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state I/Os with Enabled Internal Pull-downs) The data rate of all the output streams are programmed through the "Data Rate Selection Register" on page 31. In the 2.048 Mbps mode, these pins output serial TDM data streams at 2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode, these pins output serial TDM data streams at 4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode, these pins output serial TDM data streams at 8.192 Mbps with 128 channels per frame. In the 16.384 Mbps mode, these pins output serial TDM data streams at 16.384 Mbps with 256 channels per frame.These output streams can be used as bi-directionals by programming BDH (bit 7) and BDL (bit 6) of Internal Mode Selection (IMS) register. Output Drive Enable (5 V-Tolerant Input with Internal Pull-up) This is the output enable control for STio0 - 15. When it is high, STio0 - 15 are enabled. When it is low, STio0 - 15 are tristated. Data Bus 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state I/Os) These pins form the 16-bit data bus of the microprocessor port.
B15
141
ODE
M4, N6, R6, P7, R7, N7, M8, N8, P8, R8, M9, N9, R9, N10, P9, R10
16, 18, 20, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 36, 37, 38 44
D0 - 15
N12
DTA_RDY
Data Transfer Acknowledgment_Ready (5 V-Tolerant Three-state Output) This active low output indicates that a data bus transfer is complete for the Motorola interface. For the Intel interface, it indicates a transfer is completed when this pin goes from low to high. An external pull-up resistor MUST hold this pin at HIGH level for the Motorola mode. An external pull-down resistor MUST hold this pin at LOW level for the Intel mode. Chip Select (5 V-Tolerant Input) Active low input used by the Motorola or Intel microprocessor to enable the microprocessor port access. Read/Write_Write (5 V-Tolerant Input) This input controls the direction of the data bus lines (D0 - 15) during a microprocessor access. For the Motorola interface, this pin is set high and low for the read and write access respectively. For the Intel interface, a write access is indicated when this pin goes low. Data Strobe_Read (5 V-Tolerant Input) This active low input works in conjunction with CS to enable the microprocessor port read and write operations for the Motorola interface. A read access is indicated when it goes low for the Intel interface.
R11
40
CS
N11
39
R/W_WR
R12
42
DS_RD
13
Zarlink Semiconductor Inc.
ZL50017
PBGA Pin Number K13, K15, K14, J11, J12, J13, J15, H11, J14, H12, H13, H15, G12, G13 M13 LQFP Pin Number 82, 84, 86, 87, 88, 89, 90, 91, 92, 93, 94, 96, 98, 99 41 Pin Name A0 - 13 Description
Data Sheet
Address 0 to 13 (5 V-Tolerant Inputs) These pins form the 14-bit address bus to the internal memories and registers.
MOT_INTEL
Motorola_Intel (5 V-Tolerant Input with Internal Pull-up) This pin selects the Motorola or Intel microprocessor interface to be connected to the device. When this pin is unconnected or connected to high, Motorola interface is assumed. When this pin is connected to ground, Intel interface should be used. Device Reset (5 V-Tolerant Input with Internal Pull-up) This input (active LOW) puts the device in its reset state that disables the STio0 - 15 drivers. It also preloads registers with default values and clears all internal counters. To ensure proper reset action, the reset pin must be low for longer than 1 s. Upon releasing the reset signal to the device, the first microprocessor access cannot take place for at least 500 s due to the time required to stabilize the device from the power-down state. Refer to Section Section 11.2 on page 25 for details.
G2
211
RESET
4.0
Device Overview
The device has sixteen ST-BUS/GCI-Bus inputs (STi0 - 15) and sixteen ST-BUS/GCI-Bus outputs (STio0 - 15). STio0 - 15 can also be configured as bi-directional pins, in which case STi0 - 15 will be ignored. It is a non-blocking digital switch with 1024 64 kbps channels. The ST-BUS/GCI-Bus inputs and outputs accept serial input data streams with data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps. By using Zarlink's message mode capability, microprocessor data stored in the connection memory can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS/GCI-Bus devices. The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The output data streams will be driven by and have their timing defined by FPi and CKi. A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate in various modes under different switching configurations. Users can use the microprocessor port to perform internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY). The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
5.0
Data Rates and Timing
The ZL50017 has 16 serial data inputs and 16 serial data outputs. All streams are programmed to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 s frame.
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Zarlink Semiconductor Inc.
ZL50017
Data Sheet
The output streams can be programmed to operate as bi-directional streams. By setting BDL (bit 6) in the Internal Mode Selection (IMS) register, the input streams 0 - 15 (STi0 - 15) are internally tied low, and the output streams 0 - 15 (STio0 - 15) are set to operate in a bi-directional mode.The input data rate is set on a per-stream basis by programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input Control Register 0 - 15 (SICR0 - 15). The output data rate is set on a per-stream basis by programming STO[n]DR3 - 0 (bits 3 - 0) in the Stream Output Control Register 0 - 15 (SOCR0 - 15). The output data rates do not have to match or follow the input data rates. The maximum number of channels switched is limited to 1024 channels. If all 16 input streams were operating at 8.192 Mbps (128 channels per stream), this would result in 2048 channels. Memory limitations prevent the device from operating at this capacity. A maximum capacity of 1024 channels will occur if four streams are operating at 16.384 Mbps, eight streams are operating at 8.192 Mbps or all sixteen streams are operating at 4.096 Mbps. With all streams operating at 2.048 Mbps, the capacity will be reduced to 512 channels. It should be noted that only full streams can be enabled, the device does not allow partial streams configuration (i.e., cannot have all the streams operating at 16.384 Mbps but only access the half the channels).
5.1
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The frequency of the input clock (CKi) for the ZL50017 must be at least twice the input/output data rate. For example, if the input/output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz. Following the example above, if the input/output data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz.The only exception to this is for 16.384 Mbps input/output data. In this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) are used to program the width of the input frame pulse and the frequency of the input clock supplied to the device. Highest Input or Output Data Rate 16.384 Mbps or 8.192 Mbps 4.096 Mbps 2.048 Mbps
CKIN 1-0 Bits 00 01 10
Input Clock Rate (CKi) 16.384 MHz 8.192 MHz 4.096 MHz
Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse)
Table 1 - CKi and FPi Configurations The ZL50017 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
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Zarlink Semiconductor Inc.
ZL50017
Data Sheet
ST-BUS GCI-Bus
FPi (244 ns) FPINP = 0 FPINPOS = 0 FPi (244 ns) FPINP = 1 FPINPOS = 0 FPi (244 ns) FPINP = 0 FPINPOS = 1 FPi (244 ns) FPINP = 1 FPINPOS = 1 CKi (4.096 MHz) CKINP = 0 CKi (4.096 MHz) CKINP = 1 Channel 0 STi (2.048 Mbps) Channel 31
0
7
6
1
0
7
Figure 4 - Input Timing when CKIN1 - 0 bits = "10" in the CR
ST-BUS GCI-Bus
FPi (122 ns) FPINP = 0 FPINPOS = 0 FPi (122 ns) FPINP = 1 FPINPOS = 0 FPi (122 ns) FPINP = 0 FPINPOS = 1 FPi (122 ns) FPINP = 1 FPINPOS = 1 CKi (8.192 MHz) CKINP = 0 CKi (8.192 MHz) CKINP = 1 Channel 0 STi (4.096 Mbps) Channel 63
1
0
7
6
5
4
2
1
0
7
6
Figure 5 - Input Timing when CKIN1 - 0 bits = "01" in the CR
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Zarlink Semiconductor Inc.
ZL50017
ST-BUS FPi (61ns) FPINP = 0 FPINPOS = 0 FPi (61ns) FPINP = 1 FPINPOS = 0 FPi (61ns) FPINP = 0 FPINPOS = 1 GCI-Bus FPi (61ns) FPINP = 1 FPINPOS = 1 CKi (16.384 MHz) CKINP = 0 CKi (16.384 MHz) CKINP = 1 Channel 0 STi (8.192 Mbps) STi (16.384 Mbps) Channel N = 127
Data Sheet
107654 321
Channel 0
54 3 2 1 0 7 65
Channel N = 255
321076543210765432
321076543210765432
Figure 6 - Input Timing when CKIN1 - 0 = "00" in the CR
5.2
ST-BUS and GCI-Bus Timing
The ZL50017 is capable of operating using either the ST-BUS or GCI-Bus standards. By default, the ZL50017 is configured for ST-BUS input and output timing. To set the input timing to conform to the GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set.
6.0
Data Input Delay and Data Output Advancement
Various registers are provided to adjust the input delay and output advancement for each input and output data stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream. If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams. By default, the sampling point is set to the 3/4-bit location. The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4 bit increment. By default, there is 0 output bit advancement. Although input delay or output advancement features are available on streams which are operating in bi-directional mode it is not recommended, as it can easily cause bus contention. If users require this function, special attention must be given to the timing to ensure contention is minimized.
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Zarlink Semiconductor Inc.
ZL50017
6.1 Input Bit Delay Programming
Data Sheet
The input bit delay programming feature provides users with the flexibility of handling different wire delays when designing with source streams for different devices. By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream Input Control Register 0 - 15 (SICR0 - 15) as described in Table 10 on page 32. The input bit delay can range from 0 to 7 bits.
FPi Last Channel Channel 0 Channel 1 Channel 2
STi[n] Bit Delay = 0 (Default)
432107654321076543210765432
Bit Delay = 1 Last Channel Channel 2
STi[n] Bit Delay = 1
Channel 0
Channel 1
543210765432107654321076543
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 7 - Input Bit Delay Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50017
6.2 Input Bit Sampling Point Programming
Data Sheet
In addition to the input bit delay feature, the ZL50017 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 15 (SICR0 - 15). For input streams the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position.
FPi Sampling Point = 3/4 Bit Channel 0
STi[n] STIN[n]SMP1-0 = 00 2, 4 or 8 Mbps - Default
Last Channel
2
1
0
7
6
Sampling Point = 1/4 Bit Channel 0
5
STi[n] STIN[n]SMP1-0 = 01 (2, 4 or 8 Mbps) STi[n] STIN[n]SMP1-0 = 10 2, 4 or 8 Mbps STIN[n]SMP1-0 = 00 16 Mbps - Default STi[n] STIN[n]SMP1-0 = 11 2, 4 or 8 Mbps STIN[n]SMP1-0 = 10 16 Mbps
Last Channel
1
0
Last Channel
7
6
5
Sampling Point = 1/2 Bit Channel 0
1
Last Channel
0
7
6
5
Sampling Point = 4/4 Bit Channel 0
2
1
0
7
6
5
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively
Figure 8 - Input Bit Sampling Point Programming
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Zarlink Semiconductor Inc.
ZL50017
Data Sheet
The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to control the sampling point in the Stream Input Control Register 0 - 15 (SICR0 - 15).
Nominal Channel n Boundary Nominal Channel n+1 Boundary
STi[n]
0
7
6
5
4
3
2
1
0
7 111 11 111 00 111 10 111 01 110 11 110 00 110 10 110 01 101 11 101 00 101 10 101 01 100 11 100 00 100 10 100 01
000 01 000 10 000 00 (Default) 000 11 001 01 001 10 001 00 001 11 010 01 010 10 010 00 010 11 011 01 011 10 011 00 011 11
The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay. The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset. Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point. Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point).
Figure 9 - Input Bit Delay and Factional Sampling Point
6.3
Output Advancement Programming
This feature is used to advance the output data of individual output streams with respect to the input frame boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output Control Register 0 - 15 (SOCR0 - 15). By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the input frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4) of the Stream Output Control Register 0 - 15 (SOCR0 - 15) as described in Table 11 on page 33. The output bit advancement can vary from 0 to 7 bits.
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Zarlink Semiconductor Inc.
ZL50017
FPi
Data Sheet
Last Channel STio[n] Bit Adv = 0 (Default)
Channel 0
Channel 1
Channel 2
432107654321076543210765432
Bit Advancement = 1 Last Channel Channel 0 Channel 1 Channel 2
STio[n] Bit Adv = 1
321076543210765432107654321
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 10 - Output Bit Advancement Timing Diagram (ST-BUS)
6.4
Fractional Output Bit Advancement Programming
In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the serial data output pins. By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the Stream Output Control Register 0 - 15 (SOCR0 - 15). For all streams the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits.
FPi
Last Channel STio[n] STo[n]FA1-0 = 00 (Default)
Channel 0
2
1
Last Channel
0
7
6
Channel 0
5
Fractional Bit Advancement = 1/4 Bit
STio[n] STo[n]FA1-0 = 01 (2, 4 or 8 Mbps) STio[n] STo[n]FA1-0 = 10 (2, 4 or 8 Mbpa) STo[n]FA1-0 = 01 (16Mbps)
1
0
7
6
5
4
Fractional Bit Advancement = 1/2 Bit Last Channel Channel 0
1
0
7
6
5
4
Fractional Bit Advancement = 3/4 Bit STio[n] STo[n]FA1-0 = 11 (2, 4 or 8 Mbps) Last Channel Channel 0
1
0
7
6
5
4
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 11 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50017
7.0 Data Delay Through the Switching Paths
Data Sheet
The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform timeslot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum delay between input and output data. In wideband data applications, select constant delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected by the V/C (bit 14) in the Connection Memory Low when CMM = 0.
7.1
Variable Delay Mode
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for voice applications where the minimum throughput delay is more important than frame integrity. The delay through the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN (bit 4) in the Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0. If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid. In variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams. m = input channel number n = output channel number T = Delay between input and output n-m <= 0 1 frame - (m-n) 0 < n-m < 7 STio < STi 1 frame + (n-m) Table 2 - Delay for Variable Delay Mode For example, if Stream 4 Channel 2 is switched to Stream 5 Channel 9 with variable delay, the data will be output in the same 125 s frame. Contrarily, if Stream 6 Channel 1 is switched to Stream 9 Channel 3, the information will appear in the following frame.
Frame N Frame N + 1
n-m = 7 STio >= STi n-m
n-m > 7
STi4 CH2
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STio5 CH9
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STi6 CH1
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STio9 CH3
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127 or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively.
Figure 12 - Data Throughput Delay for Variable Delay
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Zarlink Semiconductor Inc.
ZL50017
7.2 Constant Delay Mode
Data Sheet
In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 channel delay if the last channel on a stream is switched to the first channel of a stream. The maximum delay is 3 frames - 1 channel. This occurs when the first channel of a stream is switched to the last channel of a stream. The constant delay mode is available for all output channels. The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (m) and output channel number (n). The data throughput delay (T) is: T = 2 frames + (n - m) The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay mode.
Frame N Frame N + 1 Frame N + 2
STi
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STio
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STi
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STio
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127 or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively.
Figure 13 - Data Throughput Delay for Constant Delay
8.0
Connection Memory Description
The connection memory consists of two blocks, Connection Memory Low (CM_L). The CM_L is 16 bits wide and is used for channel switching and other special modes. Each connection memory location of the CM_L or CM_H can be read or written via the 16 bit microprocessor port within one microprocessor access cycle. See Table 12 on page 34 for the address mapping of the connection memory. Any unused bits will be reset to zero on the 16-bit data bus. For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source (input) stream address. When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50017 will operate in one of the special modes described in Table 14 on page 36. When the per-channel message mode is enabled, MSG7 - 0 (bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial data stream as message output data.
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9.0 Connection Memory Block Programming
Data Sheet
This feature allows for fast initialization of the connection memory after power up.
9.1
Memory Block Programming Procedure
1. Set MBPE (bit 3) in the Control Register (CR) from low to high. 2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded into CM_L. 3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The values stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15 - 3). The following tables show the resulting values that are in the CM_L and CM_H connection memory locations. Bit Value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 BPD2 1 BPD1 0 BPD0
Table 3 - Connection Memory Low After Block Programming It takes at least two frame periods (250 s) to complete a block program cycle. MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming process has completed. MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block programming process. This is not an automatic action taken by the device and must be performed manually. Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low.
10.0
Microprocessor Port
The device provides access to the internal registers, connection memories and data memories via the microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY). The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be used and D15 - 8 will output zeros. For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros. Refer to Figure 15 on page 39, Figure 16 on page 40, Figure 17 on page 41 and Figure 18 on page 42 for the microprocessor timing.
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11.0
* * * *
Data Sheet
Device Reset and Initialization
The RESET pin is used to reset the ZL50017. When this pin is low, the following functions are performed: synchronously puts the microprocessor port in a reset state tristates the STio0 - 15 outputs preloads all internal registers with their default values (refer to the individual registers for default values) clears all internal counters
11.1
Power-up Sequence
The recommended power-up sequence is for the VDD_IO supply (normally +3.3 V) to be established before the power-up of the VDD_CORE supply (normally +1.8 V). The VDD_CORE supply may be powered up at the same time as VDD_IO, but should not "lead" the VDD_IO supply by more than 0.3 V.
11.2
Device Initialization on Reset
Upon power up, the ZL50017 should be initialized as follows: * * * * * * * Set the ODE pin to low to disable the STio0 - 15 outputs Set the TRST pin to low to disable the JTAG TAP controller Reset the device by pulsing the RESET pin to zero for longer than 1 s After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the device to stabilize from the power down state before the first microprocessor port access can occur Wait at least 500 s prior to the next microport access (see Note below) Use the block programming mode to initialize the connection memory Release the ODE pin from low to high after the connection memory is programmed
Note: If CKi is 16.384 MHz, the waiting time is 500 s; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the waiting time is 2 ms.
11.3
Software Reset
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset SRSTSW (bit 1) in the Software Reset Register (SRR).
12.0
JTAG Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
12.1
Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50017 test functions. It consists of three input pins and one output pin as follows: * Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic.
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Zarlink Semiconductor Inc.
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*
Data Sheet
Test Mode Selection Inputs (TMS) - The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to high when it is not driven from an external source. Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. The registers are described in a subsequent section. The received input data is sampled at the rising edge of the TCK pulse. This pin is internally pulled to high when it is not driven from an external source. Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or test data register are serially shifted out towards TDo. The data from TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo driver is set to a high impedance state. Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to high when it is not driven from an external source.
*
*
*
12.2
Instruction Register
The ZL50017 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDi and TDo during data register scanning.
12.3
Test Data Registers
As specified in the IEEE-1149.1 standard, the ZL50017 JTAG interface contains three test data registers: * * * The Boundary-Scan Register - The Boundary-Scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the ZL50017 core logic. The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from TDi to TDo. The Device Identification Register - The JTAG device ID for the ZL50017 is 0C36114BH Version Part Number Manufacturer ID LSB <31:28> <27:12> <11:1> <0> 0000 1100 0011 0110 0001 0001 0100 101 1
12.4
BSDL
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE-1149.1 test interface.
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Zarlink Semiconductor Inc.
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13.0 Register Address Mapping
CPU Access R/W R/W R/W R/W R Only R/W R/W Control Register Internal Mode Selection Register Software Reset Register Data Rate Selection Register Internal Flag Register Stream Input Control Registers 0 - 15 Stream Output Control Registers 0 - 15 Register Name Abbreviation CR IMS SRR DRSR IFR SICR0 - 15 SOCR0 - 15
Data Sheet
Address A13 - A0 0000H 0001H 0002H 0008H 0010H 0100H 010FH 0200H 020FH
Reset By Switch/Hardware Switch/Hardware Hardware Only Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware
Table 4 - Address Map for Registers (A13 = 0)
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14.0 Detailed Register Description
Data Sheet
External Read/Write Address: 0000H Reset Value: 0000H 15
0
14
0
13
0
12
0
11
0
10
0
9
FPIN POS
8
CKINP
7
FPINP
6
CKIN 1
5
CKIN 0
4
VAR EN
3
MBPE
2
OSB
1
MS1
0
MS0
Bit 15 - 10 9
Name Unused FPINPOS
Description Reserved. In normal functional mode, these bits MUST be set to zero. Input Frame Pulse (FPi) Position When this bit is low, FPi straddles frame boundary (as defined by ST-BUS). When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus) Clock Input (CKi) Polarity When this bit is low, the CKi falling edge aligns with the frame boundary. When this bit is high, the CKi rising edge aligns with the frame boundary. Frame Pulse Input (FPi) Polarity When this bit is low, the input frame pulse FPi has the negative frame pulse format. When this bit is high, the input frame pulse FPi has the positive frame pulse format. Input Clock (CKi) and Frame Pulse (FPi) Selection
CKIN1 - 0 00 01 10 11 FPi Active Period 61 ns 122 ns 244 ns Reserved CKi 16.384 MHz 8.192 MHz 4.096 MHz
8
CKINP
7
FPINP
6-5
CKIN1 - 0
The MODE_4M0 and MODE_4M1 pins, as described in "Pin Description" on page 9, should also be set to define the input clock mode. 4 VAREN Variable Delay Mode Enable When this bit is low, the variable delay mode is disabled on a device-wide basis. When this bit is high, the variable delay mode is enabled on a device-wide basis. Memory Block Programming Enable When this bit is high, the connection memory block programming mode is enabled to program the connection memory. When it is low, the memory block programming mode is disabled. Table 5 - Control Register (CR) Bits
3
MBPE
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Zarlink Semiconductor Inc.
ZL50017
External Read/Write Address: 0000H Reset Value: 0000H 15
0
Data Sheet
14
0
13
0
12
0
11
0
10
0
9
FPIN POS
8
CKINP
7
FPINP
6
CKIN 1
5
CKIN 0
4
VAR EN
3
MBPE
2
OSB
1
MS1
0
MS0
Bit 2
Name OSB
Description Output Stand By Bit: This bit enables the STio0 - 1 serial outputs. The following table describes the HiZ control of the serial data outputs:
RESET Pin 0 1 1 1 1 SRSTSW (in SRR) X 1 0 0 0 ODE Pin X X 0 1 1 OSB Bit X X X 0 1 STio0 - 15 HiZ HiZ HiZ HiZ Active (Controlled by CM)
Note: Unused output streams are tristated (STio = HiZ). Refer to SOCR0 - 15 (bit 2 - 0). 1-0 MS1 - 0 Memory Select Bits These two bits are used to select connection memory low, connection high or data memory for access by CPU:
MS1 - 0 00 01 10 11 Memory Selection Connection Memory Low Read/Write Reserved Data Memory Read Reserved
Table 5 - Control Register (CR) Bits (continued)
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Data Sheet
External Read/Write Address: 0001H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 STIO_ PD_EN 7 0 6 BD 5 0 4 0 3 BPD 2 2 BPD 1 1 BPD 0 0 MBPS
Bit 15 - 9 8
Name Unused STIO_PD_ EN Unused BD
Description Reserved. In normal functional mode, these bits MUST be set to zero. STio Pull-down Enable When this bit is low, the pull-down resistors on all STio pads will be disabled. When this bit is high, the pull-down resistors on all STio pads will be enabled. Reserved. In normal functional mode, these bits MUST be set to zero. Bi-directional Control
BDL 0 STio0 - 15 Operation normal operation: STi0-15 are inputs STio0-15 are outputs bi-directional operation: STi0-15 tied low internally STio0-15 are bi-directional
7 6
1
5-4 3-1
Unused BPD2 - 0
Reserved. In normal functional mode, these bits MUST be set to zero. Block Programming Data These bits refer to the value to be loaded into the connection memory, whenever the memory block programming feature is activated. After the MBPE bit in the Control Register is set to high and the MBPS bit in this register is set to high, the contents of the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3 of the Connection Memory Low. Memory Block Programming Start: A zero to one transition of this bit starts the memory block programming function. The MBPS and BPD2 - 0 bits in this register must be defined in the same write operation. Once the MBPE bit in the Control Register is set to high, the device requires two frames to complete the block programming. After the programming function has finished, the MBPS bit returns to low, indicating the operation is completed. When MBPS is high, MBPS or MBPE can be set to low to abort the programming operation. Whenever the microprocessor writes a one to the MBPS bit, the block programming function is started. As long as this bit is high, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting. Table 6 - Internal Mode Selection Register (IMS) Bits
0
MBPS
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Zarlink Semiconductor Inc.
ZL50017
Data Sheet
External Read/Write Address: 0002H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 SRST SW 0 0
Bit 15 - 2 1
Name Unused SRSTSW
Description Reserved In normal functional mode, these bits MUST be set to zero. Software Reset Bit for Switch When this bit is low, switching blocks are in normal operation. When this bit is high, switching blocks are in software reset state. Refer to Table 12, "Address Map for Registers (A13 = 0)" on page 32 for details regarding which registers are affected. Reserved In normal functional mode, these bits MUST be set to zero. Table 7 - Software Reset Register (SRR) Bits
0
Unused
External Read/Write Address: 0008H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 DR3 2 DR2 1 DR1 0 DR0
Bit 15 - 4 3-0
Name Unused DR3 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Input/Output Data Rate Selection Bits: These bits set the data rate for both input and output streams
DR3 - 0 0000 0001 0010 0011 0100 0101 - 1111 STio0 - 15 Operation Reserved 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps Reserved
Table 8 - Data Rate Selection Register
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Data Sheet
External Read Address: 0010H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PERR
Bit 15 - 1 0
Name Unused PERR
Description Reserved In normal functional mode, these bits are zero. Program Error (Read Only) This bit is set high when the total number of input/output channels is programmed to be more than the maximum capacity of 1024, in which case the input/output channels beyond the maximum capacity should be disabled.This bit will be cleared automatically after the total number of active streams/channels is correctly programmed to be 1024 channels or below. Table 9 - Internal Flag Register (IFR) Bits - Read Only
External Read/Write Address: 0100H - 010FH Reset Value: 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
STIN[n] BD2
STIN[n] BD1
STIN[n] BD0
STIN[n] SMP1
STIN[n] SMP0
0
0
0
STIN[n] EN
Bit
15 - 9 8-6
Name Unused STIN[n]BD2 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Input Stream[n] Bit Delay Bits. The binary value of these bits refers to the number of bits that the input stream will be delayed relative to FPi. The maximum value is 7. Zero means no delay. Input Data Sampling Point Selection Bits
STIN[n]SMP1-0 00 01 10 11 Sampling Point (2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams) 3/4 point 1/4 point 2/4 point 4/4 point 4/4 point Sampling Point 16.384 Mbps streams) 1/2 point
5-4
STIN[n]SMP1 - 0
3-1
Unused
Reserved In normal functional mode, these bits MUST be set to zero.
Table 10 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits
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Zarlink Semiconductor Inc.
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External Read/Write Address: 0100H - 010FH Reset Value: 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Data Sheet
0
0
0
0
0
0
0
0
STIN[n] BD2
STIN[n] BD1
STIN[n] BD0
STIN[n] SMP1
STIN[n] SMP0
0
0
0
STIN[n] EN
Bit 0
Name STIN[n]EN
Description Input Stream Enable Bit When this bit is high the input stream is enabled. When this bit is low the input stream is ignored
Note: [n] denotes input stream from 0 - 15.
Table 10 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits (continued)
External Read/Write Address: 0200H - 020FH Reset Value: 0000H
15 14 13 12 11 0 10 0 9 0 8 STO[n] FA1 7 STO[n] FA0 6 STO[n] AD2 5 STO[n] AD1 4 STO[n] AD0 3 0 2 0 1 0 0 STO[n] EN
0
0
0
0
Bit 15 - 9 8-7
Name Unused STO[n]FA1 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Output Stream[n] Fractional Advancement Bits
STO[n]FA1-0 00 01 10 11 Advancement (2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams) 0 1/4 bit 2/4 bit 3/4 bit Advancement (16.384 Mbps streams) 0 2/4 Reserved
6-4
STO[n]AD2 - 0
Output Stream[n] Bit Advancement Selection Bits The binary value of these bits refers to the number of bits that the output stream is to be advanced relative to FPi. The maximum value is 7. Zero means no advancement. Reserved In normal functional mode, these bits MUST be set to zero.
3-1 0
Note:
Unused STO[n]EN
Output Stream Enable Bit When this bit is high the output stream is enabled. When this bit is low the output stream is set to high impedance [n] denotes output stream from 0 - 15. Table 11 - Stream Output Control Register 0 - 15 (SOCR0 - 15) Bits
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15.0
15.1
Data Sheet
Memory
Memory Address Mappings
When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the Control Register determine the access to the data or connection memory (CM_L or CM_H).
MSB (Note 1) Stream Address (St0 - 15) A12 0 0 0 0 0 0 0 0 0 . . . . . 0 0 A11 0 0 0 0 0 0 0 0 1 . . . . . 1 1 A10 0 0 0 0 1 1 1 1 0 . . . . . 1 1 A9 0 0 1 1 0 0 1 1 0 . . . . . 1 1 A8 0 1 0 1 0 1 0 1 0 . . . . . 0 1 Stream [n] Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 Stream 8 . . . . . Stream 14 Stream 15 A7 0 0 . . 0 0 0 0 . . 0 0 . . 0 0 . . . . 1 1 A6 0 0 . . 0 0 0 0 . . 0 0 . . 1 1 . . . . 1 1 A5 0 0 . . 0 0 1 1 . . 1 1 . . 1 1 . . . . 1 1 A4 0 0 . . 1 1 0 0 1 1 . . 1 1 . . . . 1 1 Channel Address (Ch0 - 255) A3 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 . . . . 1 1 A2 0 0 . . 1 1 0 0 . 1 1 . . 1 1 . . . . 1 1 A1 0 0 . . 1 1 0 0 1 1 . . 1 1 . . . . 1 1 A0 0 1 . . 0 1 0 1 . . 0 1 . . 0 1 . . . . 0 1 Channel [n] Ch 0 Ch 1 . . Ch 30 Ch 31 (Note 2) Ch 32 Ch 33 . . Ch 62 Ch 63 (Note 3) . . Ch126 Ch 127 (Note 4) . . . . Ch 254 Ch 255 (Note 5)
A13
1 1 1 1 1 1 1 1 1 . . . . . 1 1
Notes: 1. A13 must 2. Channels 3. Channels 4. Channels 5. Channels
be high for access to data and connection memory positions. A13 must be low to access internal registers. 0 to 31 are used when serial stream is at 2.048 Mbps. 0 to 63 are used when serial stream is at 4.096 Mbps. 0 to 127 are used when serial stream is at 8.192 Mbps. 0 to 255 are used when serial stream is at 16.384 Mbps.
Table 12 - Address Map for Memory Locations (A13 = 1)
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15.2 Connection Memory Low (CM_L) Bit Assignment
Data Sheet
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in Table 13 on page 35.
15
0
14
V/C
13
0
12
SSA 3
11
SSA 2
10
SSA 1
9
SSA 0
8
SCA 7
7
SCA 6
6
SCA 5
5
SCA 4
4
SCA 3
3
SCA 2
2
SCA 1
1
SCA 0
0
CMM =0
Bit 15 14
Name Unused V/C
Description Reserved In normal functional mode, these bits MUST be set to zero. Variable/Constant Delay Control When this bit is low, the output data for this channel will be taken from constant delay memory. When this bit is set to high, the output data for this channel will be taken from variable delay memory. Note that VAREN must be set in Control Register first. Reserved. In normal functional mode, this bit MUST be set to zero. Source Stream Address The binary value of these 4 bits represents the input stream number. Source Channel Address The binary value of these 8 bits represents the input channel number. Connection Memory Mode = 0 If this is low, the connection memory is in the normal switching mode. Bit 13 1 are the source stream number and channel number.
13 12 - 9 8-1 0
Unused SSA3 - 0 SCA7 - 0 CMM = 0
Table 13 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
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Data Sheet
When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits PCC0 and PCC1 from connection memory are used to select the per-channel tristate or message mode as shown in Table 14 on page 36.
15
0
14
0
13
0
12
0
11
0
10
MSG 7
9
MSG 6
8
MSG 5
7
MSG 4
6
MSG 3
5
MSG 2
4
MSG 1
3
MSG 0
2
PCC 1
1
PCC 0
0
CMM =1
Bit 15 - 11 10 - 3 2-1
Name Unused MSG7 - 0 PCC1 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Message Data Bits 8-bit data for the message mode. Not used in the per-channel tristate. Per-Channel Control Bits These two bits control the corresponding entry's value on the STio stream.
PC C1 0 0 1 1 PC C0 0 1 0 1 Channel Output Mode Per Channel Tristate Message Mode Reserved Reserved
0
CMM = 1
Connection Memory Mode = 1 If this is high, the connection memory is in the per-channel control mode which is per-channel tristate or per-channel message mode.
Table 14 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
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16.0 DC Parameters
Data Sheet
Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 I/O Supply Voltage Core Supply Voltage Input Voltage Input Voltage (5 V-tolerant inputs) Continuous Current at Digital Outputs Package Power Dissipation Storage Temperature Symbol VDD_IO VDD_CORE VI_3V VI_5V Io PD TS - 55 Min. -0.5 -0.5 -0.5 -0.5 Max. 5.0 2.5 VDD + 0.5 7.0 15 1.5 +125 Units V V V V mA W C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 Operating Temperature Positive Supply Positive Supply Input Voltage Input Voltage on 5 V-Tolerant Inputs Sym. TOP VDD_IO VDD_CORE VI VI_5V Min. -40 3.0 1.71 0 0 Typ. 25 3.3 1.8 3.3 5.0 Max. +85 3.6 1.89 VDD_IO 5.5 Units C V V V V
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 Supply Current - VDD_CORE Supply Current - VDD_IO Input High Voltage Input Low Voltage Input Leakage (input pins) Input Leakage (bi-directional pins) Weak Pullup Current Weak Pulldown Current Input Pin Capacitance Output High Voltage Sym. IDD_CORE IDD_IO VIH VIL IIL IBL IPU IPD CI VOH VOL IOZ CO 5 2.4 0.4 5 10 -33 33 3 2.0 0.8 5 5 Min. Typ. Max. 75 40 Units mA mA V V A A A A pF V V A pF IOH = 8 mA IOL = 8 mA 0 < V < VDD 010 Output Low Voltage 11 Output High Impedance Leakage 12 Output Pin Capacitance
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
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17.0 AC Parameters
Data Sheet
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 2 CMOS Threshold Rise/Fall Threshold Voltage High Sym. VCT VHM Level 0.5 VDD_IO 0.7 VDD_IO Units V V V Conditions
3 Rise/Fall Threshold Voltage Low VLM 0.3 VDD_IO Characteristics are over recommended operating conditions unless otherwise stated.
Timing Reference Points ALL SIGNALS V HM V CT V LM
Figure 14 - Timing Parameter Measurement Voltage Levels
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Read Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time DS de-asserted time CS setup to DS falling R/W setup to DS falling Address setup to DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup to DTA Low Sym. tCSD tDSD tCSS tRWS tAS tCSH tRWH tAH tDS tDHZ tAKD ns ns 75 185 tAKH tAKZ 4 12 8 ns ns Min. 15 15 0 10 5 0 0 0 8 8 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF CL = 50 pF, RL = 1 K (Note 1) CL = 50 pF CL = 50 pF
10 Data Active to High Impedance 11 Acknowledgement delay time. From DS low to DTA low: Registers Memory
12 Acknowledgement hold time. From DS high to DTA high 13 DTA drive high to HiZ
Note 1: Note 2:
CL = 50 pF, RL = 1 K (Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 11.2 on page 25) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD tCSS
tCSH
CS
tDSD
VCT
DS R/W
VCT
tRWS
tRWH
VCT
tAS tAH
VALID ADDRESS
A0-A13
VCT
tDHZ
D0-D15
tDS
VALID READ DATA
VCT
tAKZ
DTA
tAKD
VCT
tAKH
Figure 15 - Motorola Non-Multiplexed Bus Timing - Read Access
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Zarlink Semiconductor Inc.
ZL50017
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Write Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time DS de-asserted time CS setup to DS falling R/W setup to DS falling Address setup to DS falling Data setup to DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Sym. tCSD tDSD tCSS tRWS tAS tDS tCSH tRWH tAH tDH tAKD 55 150 tAKH tAKZ 4 12 8 ns ns ns ns Min. 15 15 0 10 5 0 0 0 0 5 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF
10 Data hold from DS rising 11 Acknowledgement delay time. From DS low to DTA low: Registers Memory 12 Acknowledgement hold time. From DS high to DTA high 13 DTA drive high to HiZ
Note 1: Note 2:
CL = 50 pF, RL = 1 K (Note 1) CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 11.2 on page 25) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
tCSS
tCSH
CS
tDSD
VCT
DS R/W
VCT
tRWS tRWH
VCT
tAS tAH
VALID ADDRESS
A0-A13
tDS
VCT
tDH
D0-D15
VALID WRITE DATA
VCT
tAKZ
DTA
tAKD
VCT
tAKH
Figure 16 - Motorola Non-Multiplexed Bus Timing - Write Access
40
Zarlink Semiconductor Inc.
ZL50017
AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Read Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time RD setup to CS falling WR setup to CS falling Address setup to CS falling RD hold after CS rising WR hold after CS rising Address hold after CS rising Data setup to RDY high Data Active to High Impedance Sym. tCSD tRS tWS tAS tRH tWH tAH tDS tCSZ tAKD 175 185 tAKH tAKZ 4 12 8 ns ns ns ns Min. 15 10 10 5 0 0 0 8 7 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
10 Acknowledgement delay time. From CS low to RDY high: Registers Memory 11 Acknowledgement hold time. From CS high to RDY low 12 RDY drive low to HiZ
Note 1: Note 2:
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 11.2 on page 25) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
CS
tRS tRH
VCT
RD
tWS tWH
VCT
WR
tAS tAH
VALID ADDRESS
VCT
A0-A13
VCT
tCSZ
D0-D15
tDS
VALID READ DATA
VCT
tAKZ
RDY
tAKD tAKH
VCT
Figure 17 - Intel Non-Multiplexed Bus Timing - Read Access
41
Zarlink Semiconductor Inc.
ZL50017
AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Write Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time WR setup to CS falling RD setup to CS falling Address setup to CS falling Data setup to CS falling WR hold after CS rising RD hold after CS rising Address hold after CS rising Data hold after CS rising Sym. tCSD tWS tRS tAS tDS tWH tRH tAH tDH tAKD 55 150 tAKH tAKZ 4 12 8 ns ns ns ns Min. 15 10 10 5 0 0 0 10 5 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF
CL = 50 pF, RL = 1 K (Note 1)
10 Acknowledgement delay time. From CS low to RDY high: Registers Memory 11 Acknowledgement hold time. From CS high to RDY low 12 RDY drive low to HiZ
Note 1: Note 2:
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (Section 11.2 on page 25) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
CS
tWS tWH
VCT
WR
tRS tRH
VCT
RD
tAS tAH
VALID ADDRESS
VCT
A0-A13
tDS
VCT
tDH
D0-D15
VALID WRITE DATA
VCT
tAKZ
RDY
tAKD tAKH
VCT
Figure 18 - Intel Non-Multiplexed Bus Timing - Write Access
42
Zarlink Semiconductor Inc.
ZL50017
AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 2 3 4 5 6 7 8 9 TCK Clock Period TCK Clock Pulse Width High TCK Clock Pulse Width Low TMS Set-up Time TMS Hold Time TDi Input Set-up Time TDi Input Hold Time TDo Output Delay TRST pulse width Sym. tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW 200 Min. 100 20 20 10 10 20 60 30 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tTCKL TCK
tTCKH
tTCKP
tTMSS TMS
tTMSH
tTDIS tTDIH TDi tTDOD TDo tTRSTW TRST
Figure 19 - JTAG Test Port Timing Diagram
43
Zarlink Semiconductor Inc.
ZL50017
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz) Characteristic 1 2 3 4 5 6 7 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi Min. 40 20 20 55 27 27 61 67 34 34 3 Typ. 61
Data Sheet
Max. Units Notes 115 ns ns ns ns ns ns ns
8 CKi Input Clock Cycle to Cycle Variation tCVC 0 20 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 01 (8.192 MHz) Characteristic 1 2 3 4 5 6 7 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi Min. 90 45 45 110 55 55 122 135 69 69 3 Typ. 122 Max. Units Notes 220 ns ns ns ns ns ns ns
0 20 ns 8 CKi Input Clock Cycle to Cycle Variation tCVC Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
44
Zarlink Semiconductor Inc.
ZL50017
AC Electrical Characteristics- FPi and CKi Timing when CKIN1-0 bits = 10 (4.096 MHz) Characteristic 1 2 3 4 5 6 7 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi Min. 90 110 110 220 110 110 244 270 135 135 3 Typ. 244 Max. 420
Data Sheet
Units Notes ns ns ns ns ns ns ns
8 CKi Input Clock Cycle to Cycle Variation tCVC 0 20 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tFPIW
FPi
tFPIS tFPIH tCKIP tCKIH tCKIL
CKi
trCKI Input Frame Boundary tfCKI
Figure 20 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS)
tFPIW
FPi
tFPIS tFPIH tCKIP tCKIH tCKIL
CKi
trCKI Input Frame Boundary tfCKI
Figure 21 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus)
45
Zarlink Semiconductor Inc.
ZL50017
AC Electrical Characteristics - ST-BUS/GCI-Bus Input Timing Characteristic 1 STi Setup Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 2 STi Hold Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 3 STio Delay - Active to Active @2.048 Mbps @4.096 Mbps @8.192 Mbps @16.384 Mbps 4 STio Delay - Active to High-Z STio Delay - High-Z to Active 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 5 Output Drive Enable (ODE) Delay - High-Z to Active Output Drive Enable (ODE) Delay - Active to High-Z tZD_OD
E
Data Sheet
Sym. tSIS2 tSIS4 tSIS8 tSIS16 tSIH2 tSIH4 tSIH8 tSIH16 tSOD2 tSOD4 tSOD8 tSOD16 tDZ tZD
Min. 5 5 5 5 8 8 8 8 -6 -6 -6 -6
Typ.
Max.
Units ns ns ns ns ns ns ns ns
Test Conditions
CL = 30 pF 0 0 0 0 ns ns ns ns
-8 -8 -8 -8
0 0 0 0
ns ns ns ns
RL = 1 k, CL = 30 pF, See Note 1.
260
ns
6
tDZ_OD
260
ns
E Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing. Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
46
Zarlink Semiconductor Inc.
ZL50017
Data Sheet
FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) tSIS2 tSIH2 STi0 - 15 2.048 Mbps
Bit0 Ch31
Bit7 Ch0
Bit6 Ch0
VCT
tSIS4 tSIH4
Bit0 Ch63 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0
STi0 - 15 4.096 Mbps
VCT
tSIS8 tSIH8 STi0 - 15 8.192 Mbps
Bit1 Ch127
Bit0 Ch127
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
Bit3 Ch0
Bit2 Ch0
Bit1 Ch0
Bit0 Ch0
VTT VCT
Input Frame Boundary tSOD2/tDZ/tZD STio0 - 15 2.048 Mbps
Bit7 Ch31 Bit0 Ch0 Bit1 Ch0
VCT
tSOD4/tDZ/tZD STio0 - 15 4.096 Mbps
Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0
VCT
tSOD8/tDZ/tZD STio0 - 15 8.192 Mbps
Bit6 Ch127 Bit7 Ch127 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0
VCT
tSOD16/tDZ/tZD STio0 - 15 16.384 Mbps
Bit5 Bit6 Bit7 Bit0 Ch255 Ch255 Ch255 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0 Bit0 Ch1 Bit1 Ch1 Bit2 Ch1 Bit3 Ch1 Bit4 Ch1 Bit5 Ch1
VCT
Figure 22 - ST-BUS Input and Output Timing Diagram when Operated at 2, 4, 8 and 16 Mbps
47
Zarlink Semiconductor Inc.
ZL50017
Data Sheet
FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) tSIS2 tSIH2 STi0 - 15 2.048 Mbps
Bit7 Ch31
Bit0 Ch0
Bit1 Ch0
VCT
tSIS4 tSIH4
Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0
STi0 - 15 4.096 Mbps
VCT
tSIS8 tSIH8 STi0 - 15 8.192 Mbps
Bit6 Ch127
Bit7 Ch127
Bit0 Ch0
Bit1 Ch0
Bit2 Ch0
Bit3 Ch0
Bit4 Ch0
Bit5 Ch0
Bit6 Ch0
Bit7 Ch0
VTT VCT
Input Frame Boundary tSOD2 STio0 - 15 2.048 Mbps
Bit7 Ch31 Bit0 Ch0 Bit1 Ch0
VCT
tSOD4 STio0 - 15 4.096 Mbps
Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0
VCT
tSOD8 STio0 - 15 8.192 Mbps
Bit6 Ch127 Bit7 Ch127 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0
VCT
tSOD16 STio0 - 15 16.384 Mbps
Bit5 Bit6 Bit7 Bit0 Ch255 Ch255 Ch255 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0 Bit0 Ch1 Bit1 Ch1 Bit2 Ch1 Bit3 Ch1 Bit4 Ch1 Bit5 Ch1
VCT
Figure 23 - GCI-Bus Input and Output Timing Diagram when Operated at 2, 4, 8 and 16 Mbps
48
Zarlink Semiconductor Inc.
b
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 214440 26June03
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
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